1. Field of the Invention
The present invention relates to an active matrix display device, and more particularly, to an active matrix display device capable of preventing degradation.
2. Description of the Related Art
In general, display devices, such as liquid crystal displays (LCDs) or organic light emitting diodes (OLEDs), that display images by driving pixels arranged in an active matrix configuration are actively researched. In particular, the LCD displays desired images by supplying data voltages corresponding to image information to pixels arranged in the active matrix configuration to adjust light transmittance through the liquid crystal layer. For this purpose, the LCD is provided with a liquid crystal panel having pixels arranged in a matrix configuration, and a driving circuit for driving the liquid crystal panel.
The liquid crystal panel includes a plurality of gate lines, a plurality of data lines perpendicularly crossing the gate lines, and pixel regions defined by the gate lines and the data lines. In each pixel region, a thin film transistor (TFT) and a pixel electrode connected with the TFT are provided. A gate of the TFT is connected with the gate line. A source of the TFT is connected with the data line and a drain of the TFT is connected with the pixel electrode.
The driving circuit includes a gate driver for sequentially supplying output signals (for example, gate signals) to the gate lines of the liquid crystal panel, and a data driver for supplying data voltages to the data lines of the liquid crystal panel. The gate driver sequentially supplies output signals to the gate lines such that pixels on one line are selected. The data driver supplies data voltages to the data lines such that the supplied data voltages are applied to the selected pixels. Thus, the LCD displays desired images by controlling light transmittance through the liquid crystal layer using an electric field depending on the data voltages applied to each pixel.
Recently, to lower the fabrication cost, a driver built-in LCD in which the gate driver and/or the data driver are/is built-in has been developed. In such a driver built-in LCD, the gate driver is fabricated concurrently with the liquid crystal panel while the liquid crystal panel is fabricated. Alternatively, the data driver may be built in the driver built-in LCD.
FIG. 1 is a block diagram of a gate driver according to the related art. The gate driver is provided with a plurality of shift registers for sequentially supplying output signals to each gate line, as shown in FIG. 1. The data driver may also be provided with a plurality of shift registers. FIG. 2 is a detailed circuit diagram of the shift register of FIG. 1. Although FIG. 2 shows only the first shift register representatively, the remaining shift registers ST2 to STn correspond to simple modification of the first shift register ST1, and accordingly will be sufficiently understood from a description of the construction for the first shift register ST1. FIG. 3 is a voltage waveform of the shift register shown in FIG. 1.
As further shown in FIG. 1, the gate driver includes a plurality of shift registers ST1 to STn coupled in cascade. The first shift register ST1 is coupled to a start pulse (SP) input line 5 and remaining shift registers ST2 to STn are connected to an output terminal of a previous shift register. All of the shift registers ST1 to STn are coupled to three input lines among the four clock signals C1 to C4. As shown in FIG. 3, the four clock signals C1 to C4 are supplied in such a manner that their phases are sequentially delayed to be immediately one after another. Each of the shift registers ST1 to STn shifts the start pulse SP by one clock pulse using three clock signals among the four clock signals C1 to C4 and then output the start pulse SP. Output signals Vg1 to Vgn respectively output from the shift registers ST1 to STn are sequentially supplied to corresponding gate lines GL1 to GLn and at the same time supplied as start pulses to the next shift register.
The gate driver includes the plurality of shift registers ST1 to STn respectively coupled to the gate lines GL1 to GLn. The shift registers ST1 to STn are, as shown in FIG. 2, coupled in cascade to shift the start pulse SP by one clock pulse, thereby sequentially supplying output signals to the gate lines GL1 to GLn. In detail, the start pulse SP is input into the first shift register ST1, and output signals Vg1 to Vgn−1 of the shift registers of a previous stage are input into the 2nd shift register ST2 to the n-th shift register STn. These shift registers ST1 to STn receive three clock signals among the first to fourth clock signals C1 to C4 whose phases are sequentially delayed. The shift registers ST1 to STn shift the start pulse SP by one clock pulse using the input three clock signals such that the output signals Vg1 to Vgn are sequentially output.
Referring to FIG. 2, the first shift register ST1 includes a first control part 11 for controlling node Q according to the fourth clock signal C4, a second control part 13 for controlling node QB in response the third clock signal C3 or the start pulse SP, and an output part 15 that selects and outputs any one of the first clock signal C1 and a first supply voltage VSS selected by a voltage of node Q or a voltage of node QB. The first control part 11 controls the node Q such that the first clock signal C1 is output through a sixth transistor T6 of the output part 15 and is supplied as the first output signal Vg1 through the first gate line GL1. For this operation, the first control part 11 includes a first diode-connected transistor T1 coupled to the start pulse SP input line 5, and a second transistor T2 coupled to the first transistor T1, the fourth clock signal C4 and the node Q.
The second control part 13 controls the node QB such that the first supply voltage VSS is output through a seventh transistor T7 of the output part 15 and is then supplied as the first output signal Vg1 through the first gate line GL1. For this operation, the second control part 13 includes a fourth transistor T4 coupled to an input line 6 of a second supply voltage VDD, the input line 3 of the third clock signal C3, and the node QB, and a fifth transistor T5 coupled to the node QB, the start pulse SP input line 5, and an input line 7 of the first supply voltage VSS.
The output part 15 includes a sixth transistor T6 for selecting the first clock signal C1 in response to a voltage of the node Q and supplying the selected first clock signal C1 to the first gate line GL1, and a seventh transistor T7 for selecting the first supply voltage VSS in response a voltage of the node QB and supplying the selected supply voltage VSS to the first gate line GL1. The first control part 11 further includes a third transistor T3 coupled to the node Q, the node QB, and the input line 7 of the first supply voltage VSS, for controlling the node QB in a dual operation together with the seventh transistor T7.
In the first shift register ST1, the first to fourth clock signals C1 to C4, whose phases sequentially follow one after the other, are supplied, as shown in FIG. 3. The fourth clock signal C4 has a phase synchronized with the start pulse SP. The start pulse SP and the first to fourth clock signals C1 to C4 have a voltage swing in a range of −5V to 20V. In other words, the start pulse SP and the first to fourth clock signals C1 to C4 having a voltage of −5V are applied during a normal operation period while the start pulse SP and the first to fourth clock signals C1 to C4 having a voltage of 20V are applied for a pulse-on period. Hereinafter, the voltage of −5V is referred to as “low-state voltage” and the voltage of 20V is referred to as “high-state voltage”. The first supply voltage VSS provides a low-state voltage of −5V, and the second supply voltage VDD provides a high-state voltage of 20V. The first and second supply voltages are always a constant DC voltage. The first period represents a period of the fourth clock signal C4, the second period second represents a period of the first clock signal C1, the third period represents a period of the second clock signal C2, and the fourth period represents a period of the third clock signal.
Operations of the first shift register ST1 will now be described with reference to the waveforms of FIG. 3. In the first period, when the start pulse SP and the fourth clock signal C4 become a high-state voltage at the same time, the first and second transistors T1 and T2 are turned on, so that a voltage of about 20V is applied to the node Q. As a result, the sixth transistor T6 whose gate is coupled to the node Q is slowly turned on. In addition, the fifth transistor T5 is turned on as a result of the start pulse SP at a high-state voltage, so that a low-state voltage of −5V is provided from the input line 7 of the first supply voltage VSS to the node QB. Accordingly, the third and seventh transistors T3 and T7 each of which gate is coupled to the node QB are turned off. As a result, the low-state voltage of the first clock signal C1, i.e., −5V is supplied to the gate line GL1 of the first shift register ST1 such that the gate line GL1 is at a low-state voltage.
In the second period, when the start pulse SP and the fourth clock signal C4 become a low-state voltage and the first clock signal C1 becomes a high-state voltage, a bootstrapping phenomenon occurs due to an inner capacitor Cgs formed between gate and source of the sixth transistor T6, so that the node Q charges is charged up to 40V and becomes a reliable high-state voltage. The bootstrapping phenomenon is possible because all of the first to third transistors T1 to T3 are turned off and the node Q is in a floating state. Accordingly, the sixth transistor T6 is certainly turned on and thus the high-state voltage of 20V of the first clock signal C1 is rapidly charged to the first gate line GL1, so that the first gate line GL1 is supplied to the high-state voltage of 20V.
In the third period, when the first clock signal C1 becomes a low-state voltage and the second clock signal C2 become a high-state voltage, the voltage of the node Q drops to about 20V and the low-state voltage of −5V of the first clock signal is charged in the first gate line GL1.
In the fourth period, when the third clock signal C3 become a high-state voltage, the fourth transistors T4 is turned on, so that the second supply voltage VDD of 20V is provided to the node QB and the third and seventh transistors T3 and T7 are turned on. Accordingly, the high-state voltage of 20V previously on the node Q is changed to −5V, and the low-state voltage of −5V supplied from the input line 7 of the first supply voltage VSS via the turned on seventh transistor T7 is provided to the first gate line GL1. This low-state voltage on the first gate GL1 is maintained until the start pulse SP and the fourth clock signal C4 are supplied in the next frame.
During the second period, a high-state voltage is output through the sixth transistor T6 as a result of the node Q going to 40V. At this time, the node QB is at the low-state voltage of −5V. During the fourth period, the node Q is maintained at the low-state voltage until the start pulse SP and the fourth clock signal C4 are supplied in the next frame, and a high-state voltage is supplied to the node QB. As a result, during most periods of one frame, the node QB is maintained at the high-state voltage. When the high-state voltage continues for a long time on the node QB, the performance of the seventh transistor T7, whose gate is coupled to the node QB, degrades. If the degradation of the seventh transistor T7 is serious, the seventh transistor T7 can be fatally damaged, so that the LCD may no longer be driven. Accordingly, a desired image may not be displayed on the screen of the LCD.
The second shift register ST2 has the same construction as the first shift register ST1. The second shift register ST2 operates like the first shift register ST1 but uses the output signal Vg1 at a high-state voltage of the first shift register ST1 and clock signals, which have their phases delayed by one clock pulse as compared to the clock signals used in the first shift register ST1. Accordingly, the second shift register ST2 outputs an output signal at a high-state voltage that is shifted by one clock pulse as compared with the first shift register ST1. The remaining shift registers ST3 to STn operate like the second shift register ST2. Accordingly, the output signals Vg3 to Vgn at a high-state voltage are sequentially output to the corresponding gate lines GL3 to GLn. In other words, the high-state voltage output signals Vg1 to Vgn are sequentially output by the shift registers ST1 to STn coupled to the respective gate lines GL1 to GLn during one frame. The above operation is repeatedly performed for each subsequent frame.
In the gate driver constructed as above, the output signals VG1 to Vgn at a high-state voltage are supplied to the corresponding gate lines GL1 to GLn during a very short period of 16.67 ms. During the rest time of one frame period, the output signals VG1 to Vgn supplied to the respective gate lines GL1 to GLn are at a low-state voltage. When output signals Vg1 to Vgn at a low-state voltage are supplied, the gate of the seventh transistor T7 is still at the reliable high-state voltage (i.e., the voltage of node QB). To maintain the gate lines GL1 to GLn at the low-state voltage during most time of each frame, it is required to maintain the gate of the seventh transistor T7 at the reliable high-state voltage. Accordingly, by continuously repeating the above operations, a stress voltage is accumulated in the seventh transistor T7, so that the performance of the seventh transistor T7 degrades. FIG. 4 is a graph illustrating a cumulative stress voltage of the shift register shown in FIG. 1. As shown in FIG. 4, stress voltage accumulates from each frame and increases.
In general, the LCD deployed for a display device is expected to display images on for at least a few tens of years. However, the continuous accumulation of the stress voltage causes the degradation of the seventh transistor T7, so that threshold voltage of the seventh transistor T7 varies and mobility decreases. The device performance can deteriorate so much that it becomes difficult to precisely control the operation of the seventh transistor T7. As a result, a desired image is not displayed on the LCD screen. Also, the degradation of the seventh transistor results in a shortening of the life span for the LCD.